The Gray code is a binary code, described notably in document U.S. Pat. No. 2,632,058, which exhibits the advantage of requiring only the modification of a single bit when a number is incremented or decremented by one unit. This is not the case for the natural binary code in which, for example, passing from “3” (011) to “4” (100) requires the simultaneous changing of three bits.
In a natural binary counter, the fact of having to modify several bits at one and the same time when incrementing or decrementing can lead to the appearance of undesirable transient states, due to the fact that the lag in updating the various bits is different. Thus, when passing from “011” (3) to “100” (4), it is possible that the right bit may be updated first, then the central bit and finally the left bit. In this case, the counter passes briefly through the intermediate states “010” (2) and “000” (0). A reading of the counter performed when the latter is in such an intermediate state may therefore produce a considerable error. This leads to natural binary counters being used only in systems where it is possible to ensure synchronous reading, and to the counting rate being limited. Gray counters do not exhibit such a drawback: as a single bit changes during an increment or decrement, there is no intermediate state; even if the counter is read before its update is completed, the error made does not exceed one unit.
The table hereinbelow makes it possible to compare Gray and binary natural codes for the decimal numbers from 0 to 7:
DecimalGrayNatural binary00000001001001201101030100114110100511110161011107100111
It may be noted that, to increment a number in Gray code, it suffices to invert the rightmost possible bit which leads to a code word not used in precedence. Thus to pass from 0 (000) to 1 (001) the rightmost bit is inverted; then, to pass from 1 (001) to 2 (011) the second bit from the right is inverted (since if the rightmost bit were inverted it would yield 000, already used) and so on and so forth.
FIGS. 1A and 1B illustrate the diagram of a Gray counter known from the prior art. As shown by FIG. 1A, such a counter is composed of a plurality of cells C0, C1 . . . CN-1 connected in cascade, each generating a Gray bit bg0, bg1 . . . bgN-1 as well as an intermediate bit Z0, Z1 . . . ZN-1. Each cell receives as input the Gray bit and the intermediate bit which are generated by the previous cell (but the first cell receives as input two “1”s; the second cell receives as input a “1” instead of the intermediate bit Z0 generated by the first cell C0 and the last cell receives as input a “1” instead of the next to last Gray bit), a clock signal CK common to all the cells and a so-called “parity” bit BP which changes at each clock cycle and which equals “0” when the parity of the word bg0, bg1 . . . bgN-1 equals “0” and which equals “1” in the converse case (the bit of BPI is inverted at the input of the first cell). FIG. 1B illustrates the logic diagram of a cell C(i), where the reference BT indicates a flip-flop of “T” type.
In the circuit of FIGS. 1A and 1B, the Gray bit bgi, generated by the cell Ci, with i>0, depends on the value of the Gray bit bgi−1 and the intermediate bit Zi−1 generated by the previous cell, Ci−1. It may be realized that the depth of the “logic cone” at the input of the cell Ci depends on its order, i. It is known that the clock frequency of a digital circuit is limited by its logic cone of maximum depth; consequently, the higher the number of cells of which a conventional Gray counter is composed, the less fast it is.
Gray counters are used, inter alia, for the production of ramp analogue-digital converters, a basic diagram of which is shown in FIG. 2. A ramp converter comprises a voltage comparator CT receiving at a first input an analogue voltage signal Vs to be digitized and at a second input a voltage ramp VR(t)=V0·t/T of duration T and with V0>Vs, generated by a circuit GRT. The converter also comprises a binary—preferably Gray—counter CBG, exhibiting a first input for a triggering signal and a second input for a stopping signal, as well as a counting output (bg0 . . . bgN-1). A triggering signal D is provided both to the counter and to the ramp generator at intervals T; thus the count starts at the commencement of the ramp. The output signal of the comparator, SART is provided to the second input of the counter in the guise of stopping signal; thus the count is stopped when the ramp VR(t) exceeds the analogue input signal of the converter (in certain applications, the stopping of the count can be achieved by transferring the output of the counter to a memory element, without stopping the counter; this makes it possible to use a counter common to several converters, each having its own comparator and a common ramp generator). It is readily understood that the value displayed by the counter when the count is stopped is proportional to the value of Vs. The higher the number of bits of the Gray counter, the higher the resolution of the converter. In accordance with what was explained above, it is understood that it is necessary to accept a compromise between the pace of the converter—limited by that of the Gray counter—and its resolution.
The invention is aimed at surmounting the aforementioned drawbacks of the prior art, and more particularly at affording a Gray counter whose clock frequency—and therefore whose counting speed—does not depend on the number of bits. Such a counter is particularly appropriate for use in a ramp analogue-digital converter, although other applications are also conceivable.